1. Field of the Invention
The present invention relates to a semiconductor memory device in which a desired output signal line is held at a middle potential level by using an internal synchronous signal generated in response to change in an address signal externally applied so that fast operation is ensured.
2. Description of the Prior Art
Various kinds of semiconductor memory devices such as a dynamic type and a static type have been known. As an example of conventional semiconductor memory devices, a static RAM (Random Access Memory) is now described.
FIG. 1 is a block diagram showing an example of a structure of a conventional static RAM. Referring now to FIG. 1, a structure of the conventional static RAM is described.
Memory cells for storing information are divided into a plurality of the blocks 100a to 100c. Each memory block 100a, 100b, 100c has an identical structure and comprises a memory cell array 1 having memory cells arranged in an array, a group of pairs of bit lines 4 connected to memory cells aligned in a column direction out of memory cells included in the memory cell array 1, a group of transfer gates 7 each provided for each of the groups of pairs of bit lines 4 for transferring signals on the corresponding pairs of bit lines 4, and a sense amplifier 9 for detecting, amplifying and outputting signals applied through a transfer gate selected from the group of transfer gates 7 by a column address decoded signal 6 applied through a Y decoder 5 which decodes a column address signal externally applied. An internal synchronous circuit 19 is responsive to change in an external address signal 60 for generating an internal synchronous signal 18 and applying it to a switch select signal generator 12 as well as for generating a middle level control signal 20 and applying it to a middle level supply 21. The switch select signal generator 12 is activated in response to the internal synchronous signal 18 from the internal synchronous circuit 19 for generating a switch select signal 13 in response to a column address signal 17 and applying it to each switch circuit 11a, 11b, 11c. The switch circuits 11a to 11c are connected, respectively, through a sense amplifier output signal line 10 to the sense amplifier 9 included in each of memory cell array blocks 100a to 100c and are responsive to the switch select signal 13 from the switch select signal generator 12 for transferring an output of the corresponding sense amplifier to an output data bus 14. The middle level supply 21 is responsive to the middle level control signal 20 from the internal synchronous circuit 19 for holding the level on the output data bus 14 at a middle potential level between "H" and "L" levels. An output buffer 15 is connected to the output data bus 14 for waveform-shaping a signal on the output data bus 14 and applying it to an output terminal 16.
The operation is now described. In response to a row address signal (not shown) externally applied, a word line (not shown) is designated by the row address signal to become an active state "H", so that a single row 2 of memory cells is selected. As a result, data stored in the memory cells 3 in the selected row 2 are read out on the group of pairs of bit lines 4. At the same time, the column address decoded signal 6 is applied to the group of transfer gates 7 from the Y decoder 5 for decoding a column address signal. The group of transfer gates 7 comprises transfer gates each connected to each corresponding pair of bit lines of the group of pairs of bit lines 4, and corresponding transfer gate is rendered conductive by the column address decoded signal 6 from the Y decoder 5. As a result, data on a particular pair of bit lines out of the group of pairs of bit lines 4 is selected, and is transferred to an I/O line 8. Data on the I/O line 8 is provided to the sense amplifier 9, so that the data is amplified and is applied through the sense amplifier output signal line 10 to the switch circuit 11a. Although the operation so far described is directed to the particular memory cell array block 100a, it should be noted that the same operation is performed in the other blocks 100b and 100c. The switch circuits 11a to 11c are responsive to the switch select signals 13 applied from the switch select signal generator 12. The switch select signal generator 12 is activated by the internal synchronous signal 18 from the internal synchronous circuit 19, generates the switch select signal 13 for selecting only one of the plurality of switch circuits 11a to 11c in response to the column address signal 17, and apply it to one of the switch circuits 11a to 11c. Thus, the corresponding sense amplifier output signal line 10 is electrically connected to the output data bus 14 through a selected switch circuit. As a result, data on the sense amplifier output signal line 10 is transferred to the output data bus 14 through the selected switch circuit in a conductive state. The data is waveform-shaped in the output buffer 15 and then is transferred to the output terminal 16.
As shown in FIG. 1, a memory cell array is divided into a plurality of memory blocks 100a to 100c. Furthermore, each of the memory blocks 100a to 100c comprises the sense amplifier 9 for the reasons described in the following. More particularly, the number of memory cells included therein increases as memory capacity of the semiconductor memory device increases. Thus, the number of the pairs of bit lines 4 for which the sense amplifier 9 should have responsibility is also increased. However, if and when only one sense amplifier 9 is provided, the I/O line 8 connected thereto increases in length, parasitic capacitance depending on the interconnection length increases, and the RC delay (R: interconnection resistance, C: interconnection capacitance) of a signal increases, causing deterioration of performance so that the access time increases. In order to avoid such deterioration of performance, the number of the pairs of bit lines 4 for which a single sense amplifier 9 should be responsible is decreased by dividing a memory cell array so that the I/O line 8 may not increase in length.
With a memory cell array divided into a plurality of blocks, one of output data on the sense amplifier output signal lines 10 connected to the memory blocks 100a to 100c, respectively, as described above is selected by one of the switch circuits 11a to 11c and is transferred to the output data bus 14. However, since the output data bus 14 must be connected to all the sense amplifiers 9, parasitic capacitance depending on the interconnection length increases and thus the access time increases. In order to prevent increase of the access time due to the interconnection length of the output data bus 14, there is a method of applying forcedly to the output data bus 14 the middle potential level between "H" and "L" levels immediately before sense amplifier output data is read out to the output data bus 14, by using the middle level control signal 20 generated by the internal synchronous circuit 19 (referred to as "a method of making an output data bus a middle potential level" hereinafter).
FIG. 2 is a diagram showing timing of signals on each signal line in the semiconductor memory device for making an output data bus a middle potential level. Referring now to FIGS. 1 and 2, the operation is described. When the address signal 60 (waveform (a) in FIG. 2) changes, an output of the sense amplifier 9 (waveform (b) in FIG. 2) changes from an "H" level to an "L" level or from an "H" level to an "L" level in response to the read-out data. When the output of the sense amplifier 9 (waveform (b) in FIG. 2) changes, correspondingly the signal level on the output data bus 14 changes. When the output data bus 14 is not made a middle potential level, a change in the signal level becomes slower than that of the output of the sense amplifier 9 as shown in waveform (c) in FIG. 2, because the output data bus 14 has large parasitic capacitance depending on the interconnection length. As compared with a time point 26 where of the output of the sense amplifier 9 (waveform (b) in FIG. 2) changing from an "H" level to an "L" level and a waveform of the output of the sense amplifier 9 changing from an "L" level to an "H" level are crossing (referred to simply as a cross time point of waveforms hereinafter), a cross time point 27 of waveforms at the level of the output bus 14 (waveform (c) in FIG. 2) is slightly delayed. In order to prevent such delay, if the output data bus 14 is forced to a middle potential level by using a middle potential supply 21 controlled by the middle potential control signal 20 (waveform (d) in FIG. 2) immediately before the cross time point 26 of the outputs of the sense amplifier 9, the signal waveform on the output data bus 14 is formed as shown in waveform (b) in FIG. 2, so that the delay of a cross time point 29 of the signal waveforms on the output data bus 14 from the cross time point 26 of the outputs of the sense amplifier 9 can be extremely decreased. Hence, V.sub.M shown in waveform (e) in FIG. 2 represents a middle potential level. As a result, the signal waveform provided to the output terminal 16 through the output buffer 15 is formed as shown in waveform (h) in FIG. 2, so that the access time T2 can be shorter than the access time T1 when the output data bus 14 is not made a middle potential level (waveform (g) in FIG. 2). In the above description, the signal waveforms of the internal synchronous signal 18 (waveform (f) in FIG. 2) and the middle level control signal 20 (waveform (d) in FIG. 2) are shown only by way of an example, and the middle potential level is provided to the output data bus 14 during a period T.
A conventional semiconductor memory device is constructed as described above. However, an input stage of the output buffer 15 generally comprises, for example, an inverter, a combinational circuit including an NAND gate, an NOR gate or the like, or a latch circuit. Any circuit has an input logical threshold (an input level required for changing an output level. For Example, if the signal level on the output data bus 14 is at a higher potential level than the input logical threshold, an "L" level is outputted to the next stage, and if the signal level on the output data bus 14 is data lower potential level than the input logical threshold, an "H" level is outputted to the next stage.
In the structure of the conventional semiconductor memory device, it is extremely difficult to control the middle potential level (V.sub.M in waveform (e) in FIG. 2) to be applied to the sense amplifier output data bus 14 at the same potential level as the input logical threshold in the input stage of the output buffer 15 because of noise, variation of device characteristics or the like. Therefore, in the conventional semiconductor memory device, the level on the output data bus 14 at the time point (29 in waveform (e) in FIG. 2), when the output data bus 14 becomes the middle potential level V.sub.M, is somewhat higher or lower than the input logical threshold in the input stage of the output buffer 15. As an example, assuming that the middle potential level V.sub.M on the output data bus 14 is somewhat higher than the input logical threshold in the input stage of the output buffer 15, the input stage of the output buffer 15 always outputs an "L" level to the following stage, during the period T when the output data bus 14 is at the middle potential V.sub.M, and thus the output terminal 16 outputs an "L" (or an "H") level during the period T. As a result, as shown in waveforms (i), and (k) in FIG. 2, output noise is caused. More specifically, FIG. 2(i) shows a signal waveform at the terminal 16 when read-out data changes from an "H" to an "L" level with an address signal, waveform (j) in FIG. 2 shows a signal waveform at the output terminal 16 when read-out data changes from an "L" level to an "H" level, and waveform (k) in FIG. 2 shows a signal waveform at the output terminal 16 when read-out data continues from an "H" level to an "H" level. In waveform (j) in FIG. 2 data in the previous cycle is at an "L" level. Therefore, even if an "L" level is provided during the period T, it is identical to data in the previous cycle, so that output noise does not apparently exist. As shown in waveforms (i) to (k) in FIG. 2, an "L" level is once outputted immediately before,..true data is outputted in any case. In waveforms (i) to (k) in FIG. 2, the level at the output terminal 16 is an "L" level during the period T. However, it is the same with the case where the signal level at the output terminal 16 is an "H" level during the period T. As a result, difference in the access time between reading out of data at an "H" level and read-out of data at an "L" level is caused, and increase of the access time is caused due to change in state and increase of the consumed current is caused by flow of through-out current due to change in state.
As the prior art related to the present invention, an article by K. C. Hardee et al., entitled "A Fault-Torelant 30 ns/375mW 16k.times.1 NMOS Static RAM", IEEE Journal of Solid-State Circuits, Vol. SC-16, No. 5, October 1981, pp. 435-443 is provided.
The above prior art describes a method for equilibrating potential of bit lines of each pair of bit lines to reduce the access time. The technique is not limited to the bit line and is applicable to a data bus. However, the prior art does not disclose the technique for holding data in the previous cycle as in the present invention. Therefore, if the conventional equilibration technique is applied to the data bus, the above described problems occurs.